1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC) device, in particular, to a semiconductor IC device configured so that electrostatic breakdown of a transistor placed in the input/output side of an internal circuit is prevented.
2. Description of the Related Art
In a semiconductor IC device, as shown in FIG. 1, in order to prevent electrostatic discharge (ESD) breakdown in an internal circuit 1 caused by static electricity applied between two pads P1 and P2 including a power-supply pad and a signal input/output pad, an ESD circuit 2 is provided in series or parallel with a circuit for connecting the internal circuit 1 and the two pads P1 and P2. The ESD circuit 2 dissipates an ESD surge current (hereinafter referred to as a surge current) from a high-potential pad (for example, a signal input/output pad (I/O pad)) P1 to a low-potential pad (for example, a ground pad (GND pad)) P2. The ESD circuit 2 includes semiconductor devices such as a MOS transistor, a diode, and a thyristor. In particular, in an ESD circuit including a resistor (ballast resistor) and a MOS transistor connected in series, as disclosed in Japanese Unexamined Patent Application Publication No. 2001-110995, snap-back of a parasitic bipolar transistor caused when a surge current is applied allows the surge current to be dissipated to the GND and also allows a voltage input to the internal circuit to drop to the snap-back voltage, so that ESD breakdown of the MOS transistor of the internal circuit can be prevented. At this time, if the surge current exceeds the current at snap-back, part of the surge current flows into the internal circuit.
On the other hand, as shown in FIG. 1, the internal circuit of a semiconductor IC device often includes a matching circuit 3 for matching the impedance between the two pads P1 and P2. In many cases, the matching circuit 3 includes resistance elements of minor variations and variable resistance elements whose resistance can be finely adjusted, so as to enhance the matching accuracy. As the variable resistance elements, MOS transistors using the resistance at an ON-operation may be used. FIG. 2 shows an example of this type of conventional matching circuit. In this circuit, a resistance element R2 is connected in series to a plurality of (8 in this example) MOS transistors M31 to M38 (the sources and drains thereof are connected in parallel), and a matching adjustor 31 for selectively allowing the MOS transistors M31 to M38 to perform an ON-operation is connected. In the matching circuit including the resistance element R2 and the eight MOS transistors M31 to M38, the entire resistance, that is, the impedance of the circuit can be adjusted by connecting in series ON-resistance of at least one of the MOS transistors M31 to M38 in an ON-state to the resistance element R2. By using MOS transistors of a small gate width as the MOS transistors M31 to M38, the ON-resistance of each MOS transistor can be increased. Accordingly, the adjustment range of the impedance decreases and thus the matching accuracy can be enhanced.
For example, in the matching circuit shown in FIG. 2, a 20-Ω-resistor is used as the resistance element R2 and the MOS transistors M31 to M38 are selectively allowed to perform an ON-operation. With this arrangement, parallel-connection resistance of ON-resistance (each of which is 240 Ω) of the eight MOS transistors M31 to M38 is adjusted to 30 Ω, so that an impedance matching of 50 Ω is realized. The resistance of the resistance element R2 must be lower than the matching impedance. By decreasing the ON-resistance of the MOS transistors M31 to M38 while increasing the resistance of the resistance element R2 as much as possible, the gate width of the MOS transistors M31 to M38 increases and they occupy a very large area, which is disadvantageous for realizing a highly integrated semiconductor IC device. Therefore, in the circuit shown in FIG. 2, the resistance of the resistance element R2 is set to a smaller value and the ON-resistance of the MOS transistors M31 to M38 is set to a larger value, so as to minimize the area of the MOS transistors and to promote high integration. If the matching circuit includes only resistance elements, current consumption increases because a current constantly flows through the resistance elements. Whereas, if just the ON-resistance of the MOS transistors is used for the matching circuit, it is difficult to obtain a highly accurate impedance due to manufacture variations of the MOS transistors.
In a case where the ESD circuit disclosed in Japanese Unexamined Patent Application Publication No. 2001-110995 is connected to the above-described matching circuit, if a surge current which cannot be dissipated in the ESD circuit is applied to the matching circuit, the surge current is applied to each of the MOS transistors M31 to M38 without sufficiently being controlled by the resistance element R2 because the resistance of the resistance element R2 is 20 Ω, which is lower than the matching impedance of 50 Ω. Further, since the gate width of each of the MOS transistors M31 to M38 is small, as described above, any one of the MOS transistors performs a parasitic bipolar operation alone and the MOS transistor cannot stand a current flowing thereto. Accordingly, the MOS transistor breaks down earlier than a MOS transistor of the ESD circuit. This is because a plurality of MOS transistors in the matching circuit are not likely to perform a parasitic bipolar operation at the same time due to variations of manufacturing conditions, although the plurality of MOS transistors used in the matching circuit are manufactured under the same standard. As a result, this type of matching circuit cannot be protected by the ESD circuit, and thus the semiconductor integrated circuit including the matching circuit is broken down.